Truth Table Generator

A truth table lists the value of a Boolean expression for every combination of its inputs. With n variables there are 2ⁿ rows, conventionally ordered by counting in binary with the first variable as the most significant bit, so row 0 is all false and the last row is all true. The row index is the minterm number: rows where the expression is true are the minterms, rows where it is false are the maxterms. This tool parses your expression into a syntax tree, evaluates that tree once per row, and also evaluates each internal node so it can show the intermediate columns that make hand-checking easy.

The parser accepts the notations used in discrete mathematics, digital logic, and programming interchangeably. NOT binds tightest, then AND, XOR, OR, implication, and finally the biconditional; implication associates to the right, matching the usual textbook convention. Writing two variables next to each other (AB) or a prime after a term (A′) follows Boolean-algebra style, while words like rain and umbrella are treated as single propositional variables. The “parsed as” line shows the tree the tool actually built, which is the fastest way to catch a missing pair of parentheses.

Simplification uses the Quine–McCluskey algorithm. Minterms are grouped by their number of ones and repeatedly merged whenever two differ in exactly one bit, producing terms with don’t-care positions; anything that can no longer merge is a prime implicant. A prime-implicant chart then shows which minterms each covers. Essential prime implicants are taken first, and Petrick’s method resolves the remaining cover exactly, choosing the fewest terms and, on ties, the fewest literals. Running the same procedure on the maxterms and complementing each term gives the minimal product-of-sums.

The Karnaugh map is the visual form of the same idea. Cells are arranged in Gray-code order so that horizontal and vertical neighbours — including cells that wrap across an edge — differ in one variable. A rectangular block of 2ᵏ ones is a product term with k variables eliminated. The coloured dots on the map correspond to the minimal-SOP terms, so you can verify by eye that every 1 is covered and that no group could be enlarged. For five or more variables the map becomes hard to read, so the tool reports the algebraic result only.

The gate diagram renders the minimal SOP as a standard two-level AND–OR network: inverters on any complemented literal, one AND gate per product term, and a single OR gate collecting the terms. It is the circuit a digital-logic course expects you to draw from a simplified expression, and a useful sanity check that the literal count in the algebra matches the wiring.

Built and maintained by the runcell.dev team. Last reviewed September 2026.